1. Technical Field
The present invention generally relates to a semiconductor apparatus, and more particularly, to a stacked semiconductor apparatus.
2. Related Art
In order to improve the degree of integration of a semiconductor apparatus, a 3D (three-dimensional) semiconductor apparatus, in which a plurality of chips are stacked and packaged to increase the degree of integration, has been developed. In the 3D semiconductor apparatus, since two or more chips are vertically stacked, a maximum degree of integration may be achieved in the same area. In the 3D semiconductor apparatus, instead of improving operating frequency, a band width is increased by allocating separate channels to stacked chips.
FIG. 1 is a view schematically showing the configuration of a conventional semiconductor apparatus. In FIG. 1, the semiconductor apparatus includes first to fourth chips CHIP0 to CHIP3 and a control chip MCHIP. The control chip MCHIP may be a chip which is packaged along with the first to fourth chips CHIP0 to CHIP3 into a single package, and may perform the function of an interposer in a system-in-package including a controller.
The first to fourth chips CHIP0 to CHIP3 operate by being divided into planes. That is to say, respective chips are distinguished by planes so as to improve a band width, and separate channels are allocated to the respective planes. In FIG. 1, the first chip CHIP0 is divided into first and second planes Plane0 and Plane1, the second chip CHIP1 is divided into third and fourth planes Plane2 and Plane3, the third chip CHIP2 is divided into fifth and sixth planes Plane4 and Plane5, and the fourth chip CHIP3 is divided into seventh and eighth planes Plane6 and Plane7. The control chip MCHIP has first to eighth channels CH0 to CH7 for communicating with the first to eighth planes Plane0 to Plane7. In other words, the first channel CH0 is to communicate with the first plane Plane0 of the first chip CHIP0, and the second channel CH1 is to communicate with the second plane Plane1 of the first chip CHIP0. The remaining channels are provided to communicate with corresponding planes of corresponding chips, respectively.
The control chip MCHIP includes a plurality of ports. The plurality of ports receive signals for operating the first to fourth chips CHIP0 to CHIP3, from a controller (not shown) or a test equipment (not shown). The control chip MCHIP includes first to eighth normal ports NA0 to NA7 and first to eighth test ports DA0 to DA7. The first normal port NA0 and the first test port DA0 are connected with the first channel CH0, and the second normal port NA1 and the second test port DA1 are connected with the second channel CH1. The remaining ports are connected with corresponding channels, respectively.
The normal ports NA0 to NA7 are to receive signals for normal operations of the first to fourth chips CHIP0 to CHIP3, from the controller, and the test ports DA0 to DA7 are to receive signals for test operations of the first to fourth chips CHIP0 to CHIP3, from the controller or the test equipment. The signals include a plurality of signals such as address signals, command signals, clock signals, and so forth.
FIG. 2 is a view schematically showing the configuration of the control chip MCHIP of FIG. 1. In FIG. 2, the control chip MCHIP includes first to eighth selection units 11 to 18. The first selection unit 11 receives signals which are inputted through the first normal port NA0 and the first test port DA0, and outputs one of the signals to the first channel CH0 in response to a test mode signal TMDA. The second selection unit 12 receives signals which are inputted through the second normal port NA1 and the second test port DA1, and outputs one of the signals to the second channel CH1 in response to the test mode signal TMDA. The third selection unit 13 receives signals which are inputted through the third normal port NA2 and the third test port DA2, and outputs one of the signals to the third channel CH2 in response to the test mode signal TMDA. The fourth selection unit 14 receives signals which are inputted through the fourth normal port NA3 and the fourth test port DA3, and outputs one of the signals to the fourth channel CH3 in response to the test mode signal TMDA. The fifth to eighth selection units 15 to 18 output ones of the signals which are received through the respective ports, to the allocated channels. Since the control chip MCHIP includes the first to eighth selection units 11 to 18, the control chip MCHIP may transmit the signals inputted through the respective normal ports NA0 to NA7, to the channels CH0 to CH7 in the normal operations, and may transmit the signals inputted through the respective test ports DA0 to DA7, to the channels CH0 to CH7 in the test operations.
As described above, in the conventional semiconductor apparatus, all the selection units 11 to 18 should be connected with the normal ports NA0 to NA7 and the test ports DA0 to DA7 which are individually separated from one another. The reason to this resides in that, since the chips constituting the semiconductor apparatus operate by being divided into the planes and communicate through the separated channels, the normal operations and the test operations should be separately performed. As can be seen from the above descriptions, a large number of signals are inputted through the normal ports NA0 to NA7 and the test ports DA0 to DA7 from the controller or the test equipment. Therefore, the control chip MCHIP should have large numbers of ports and balls to receive the signals.